Physical Design Expert - Soc/ip/sub-system Design Job in Tessolve

Qualification: BE / ME / B.Tech / M.Tech in EEE/ECE/EI/CS

Experience: 8 to 15 years

No of Position: 20+ (Including 2 Leads / 2 Experts)

Location: Bangalore

Requirements:

• Must be hands-on technical expert.
• Strong written and oral communication skills.
• Experienced in deep sub-micron designs (28/14/7nm) and associated issues (manufacturability, power, signal integrity, scaling).
• Experienced in leading Hard-IP/HardMacro/SOC timing closure and physical design tasks with deep technical knowledge in all.
• Stages of the design (floor planning, placement, clock-tree-synthess CTS, routing, noise reduction/cross-talk, extraction, IR drop, IO Pad-ring, LVS/DRC and other physical and electrical checks).
• Experience in Low power and high performance design.
• Experience in designing for automotive industry.
• Be able and willing to mentor junior team members technical or otherwise.
• Should be able to lead by example.
• Be able to support periodic training session and knowledge sharing sessions.
• Able and willing to work with teams across sites and with cross-functional teams.
• Able to collaborate, extract information and deliver results.
• Should have sound understanding of all the Physical Design requirements.
• Should be able to comprehend architecture, architecture limitations from Physical Design perspective, schedule, volume of the task and personnel requirement.
• Strong debug skills and Automation savvy.
• Thorough understanding of ARM -A15/A9 (and or DSP) architecture.
• Good understanding of mixed-signal building blocks.
• Understanding of power management and its implication on physical design.
• Expert in tools Cadence Encounter/Magma Talus/Synopsys ICC, Primetime, StarXT, DRC/LVS.

Experience:

• SOC/IP/Sub-System Design.