Physical Design Job in Spectrum Consultants India Pvt Ltd
Physical Design
Spectrum Consultants India Pvt Ltd
4+ weeks ago
- Bengaluru, Bangalore Urban, Karnataka
- Not Disclosed
- Permanent
Job Summary
(2) Technologist Engineer Synthesis, DFT, PD, STA
a. DFT required, others preferred, but open to learn Synthesis and Physical design
b. Experience range: 8+ years, multiple tapeouts or strong proven candidates with lesser experience
c. DFT skillsets needed:
i. With extensive hands-on experience in DFT Scan synthesis, boundary scan, BIST and ATPG pattern generation with exposure to Cadence NCSIM, ICCR/IMC, Verdi, SVN, AccuRev & scripting languages
ii. Candidate would analyze test metrics, come up with strategies to enhance test coverage and reduce test cost
iii. Right candidate would drive DFT Architecture, design & validation end-to-end, including post silicon support and feedback yield learnings for continuous improvements
iv. This position involves in-depth understanding of the Memory Design and Logic Design, as this is for Memory Chip, that has big amount of Analog blocks, along with, digital logic and custom blocks
(3) Senior Manager/Technologist Arch, uArch, RTL, Constraints
a. General:
i. Experience range: 15+ years, multiple tapeouts or strong proven candidates with lesser experience
ii. Strong hands-on technical, with highly analytical and problem solving capabilities
iii. 5+ years team responsibilities preferred
iv. Self-motivated to look for gaps in existing process and flows, and, quick to come up with innovative solutions to existing problems
v. Think design E2E instead of only RTL
b. Specific
i. NAND experience is a strong plus
ii. Must be a fast self-learner to understand current design from RTL/docs available and take responsibility for NAND Architecture and RTL blocks
iii. Expert in working with Architects and System Engineers to micro-architect cutting edge features, implement in RTL, write & validate constraints
iv. Must be able to write testcases in SystemC, UVM environment to do specific module verification
v. Must be well versed in logic optimization, synthesis and timing analysis
vi. Must understand DFT and Physical design challenges and apply to uArch and RTL hierarchy partitioning
vii. Expert in timing, Lint, CDC quality checks
viii. Must have past experience in supporting verification team in coverage analysis and debug
ix. Mixed signal design experience is a strong plus
x. Post-silicon bring-up experience in lab is an added plus
a. DFT required, others preferred, but open to learn Synthesis and Physical design
b. Experience range: 8+ years, multiple tapeouts or strong proven candidates with lesser experience
c. DFT skillsets needed:
i. With extensive hands-on experience in DFT Scan synthesis, boundary scan, BIST and ATPG pattern generation with exposure to Cadence NCSIM, ICCR/IMC, Verdi, SVN, AccuRev & scripting languages
ii. Candidate would analyze test metrics, come up with strategies to enhance test coverage and reduce test cost
iii. Right candidate would drive DFT Architecture, design & validation end-to-end, including post silicon support and feedback yield learnings for continuous improvements
iv. This position involves in-depth understanding of the Memory Design and Logic Design, as this is for Memory Chip, that has big amount of Analog blocks, along with, digital logic and custom blocks
(3) Senior Manager/Technologist Arch, uArch, RTL, Constraints
a. General:
i. Experience range: 15+ years, multiple tapeouts or strong proven candidates with lesser experience
ii. Strong hands-on technical, with highly analytical and problem solving capabilities
iii. 5+ years team responsibilities preferred
iv. Self-motivated to look for gaps in existing process and flows, and, quick to come up with innovative solutions to existing problems
v. Think design E2E instead of only RTL
b. Specific
i. NAND experience is a strong plus
ii. Must be a fast self-learner to understand current design from RTL/docs available and take responsibility for NAND Architecture and RTL blocks
iii. Expert in working with Architects and System Engineers to micro-architect cutting edge features, implement in RTL, write & validate constraints
iv. Must be able to write testcases in SystemC, UVM environment to do specific module verification
v. Must be well versed in logic optimization, synthesis and timing analysis
vi. Must understand DFT and Physical design challenges and apply to uArch and RTL hierarchy partitioning
vii. Expert in timing, Lint, CDC quality checks
viii. Must have past experience in supporting verification team in coverage analysis and debug
ix. Mixed signal design experience is a strong plus
x. Post-silicon bring-up experience in lab is an added plus
Experience Required :
8 to 17 Years
Vacancy :
2 - 4 Hires
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